The invention relates to a circuit arrangement for the synchronization of a subordinate system, in particular a digital subscriber station, by a superordinate system, in particular a digital exchange in a pulse code modulated (PCM) telecommunication network.
Digital signals are transmitted in a PCM telecommunication network in the form of message signal blocks which comprise: (1) a prefixed synchronization word whose first bit always keeps the same value but which indicates, by changing bit combinations, at least the beginning of a superframe containing several receive/transmit periods of such message signal blocks; (2) in some cases, a plurality of bits for signalling or control; and (3) at least one message signal word. The beginning of a message signal block is identified by evaluating those bit combinations resembling a synchronization word which occur simultaneously with a "criterion" constituting an enabling time window and indicated by a separate signal. The first bit of a synchronization word is identified as the start of the message signal block.
The mentioned "criterion" ensures that message signal bit combinations, which resemble but do not constitute synchronization words and which usually occur from time to time over protracted time periods, do not lead to erroneous synchronizations. If the digital message signals of the message signal blocks are represented during transmission by signal values which can be distinguished from the signal states prevailing during the intervals between transmissions, such a criterion can be derived at the receiving end from the message signal blocks themselves by generating a receive control signal which marks the time position of the message signal block and also indicates its length. This technique is disclosed in the West German patent application No. P 28 35 605.
If, however, as is often the case the so-called AMI code (alternate mark inversion code) is used for message signal bit representation in which the "1" binary values are indicated by alternate pulses of positive and negative voltage and the "0" binary values are indicated by a zero voltage, it is not possible to produce such a receive control signal.
It has therefore been proposed to clear the synchronization system during the synchronization phase to permit an immediate resynchronization only after a counter, set to its initial position by each received bit of that binary value which the first bit of a synchronization word must have, and advanced by the transmit/receive clock, has reached a position or count corresponding to a total number of bit time periods which is greater than the time span during which bits of the other binary value can occur successively in a message signal block. After this count is reached, continued counting is prevented. For example, with the so-called HD3 code, it is ensured that no more than three bits of the binary value "0" occur successively in a message signal. If, therefore, in the proposed method the designated counter position of the counter corresponds to a time span that is greater than the sum of three bit time periods, the counter, which had been set to its initial position by a "1" bit of a message signal block, will not be able to reach this counter position for the duration of this message block because it will be reset again and again. The final counter position will instead by reached only in the interval between the reception of two message signal blocks so that, assuming absence of disturbances within such an interval, a resynchronization can actually take place only due to the occurrence of a synchronization word at the beginning of the next following message signal block. By clearing the synchronization system only at a counter position which corresponds to a time span lasting almost as long as the interval between the reception of two message signal blocks, it is ensured that any disturbances that might occur during this interval cannot lead to a false resynchronization.
In the above-mentioned mode of operation the first bit of the synchronization word sent at the beginning of the block has always the same binary value, but a second bit and possibly additional bits change their binary value after one or more transmission periods, depending on the particular situation. A superframe, comprising in the simplest case two transmission periods, is identified in this way thereby making it possible to join together in such message signal blocks any signalling bits into signalling words in addition to the actual message signal words.
It is an object of the present invention, in view of the described requirements, to provide a synchronization circuit by means of which message signal block starts, and hence correct synchronization words, can be reliably recognized. It is a further object to provide such a circuit wherein at least the beginnings of the superframes are detectable, where synchronization is achieved within the shortest possible synchronization time, and in which single disturbances remain largely ineffective. The circuit must neither effect a resynchronization during the synchronization phase due to such disturbances nor initiate a new searching process for a synchronization word during the phase of synchronous operation.